The escalating demands for high densification and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, such as 0.18 microns, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional interconnection technology, including conventional photolithographic, etching and deposition techniques.
Conventional methodology for forming patterned metal layers comprises a subtractive etching or etch back step as the primary metal patterning technique. Such a method involves the formation of a first dielectric layer on a semiconductor substrate, typically monocrystalline silicon, with conductive contacts formed therein for electrical connection with an active region on the semiconductor substrate, such as a source/drain region. A metal layer, such as aluminum or an aluminum alloy, is deposited on the first dielectric layer, and a photoresist mask is formed on the metal layer having a pattern corresponding to a desired conductive pattern. The metal layer is then etched through the photoresist mask to form the conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric layer is then applied to the resulting conductive pattern to fill in the gaps and the surface is planarized, as by conventional etching or chemical-mechanical polishing (CMP) planarization techniques.
As shown in FIGS. 1 and 2, conventional practices comprise depositing metal layer 11 on dielectric layer 10 which is typically formed on a semiconductor substrate containing an active region with transistors (not shown) After photolithography, etching is then conducted to form a patterned metal layer comprising metal features 11a, 11b, 11c and 11d with gaps therebetween. A dielectric material 12, such as spin on glass (SOG), is typically deposited to fill in the gaps between the metal features, and baked at a temperature of about 300.degree. C. to about 350.degree. C., and then cured in a verticle furnace at about 350.degree. C. to about 400.degree. C. for a period of time up to about one hour, depending upon the particular SOG material employed, to effect planarization. Another oxide is deposited by plasma enhanced chemical vapor deposition (PECVD) and then planarization is then performed, as by CMP.
As feature sizes, e.g., metal lines and interwiring spacings, shrink to 0.2 microns and below, it becomes increasingly difficult to satisfactorily fill in the interwiring spacings voidlessly and obtain adequate step coverage. It also becomes increasingly difficult to form a reliable interconnection structure. A spin on dielectric material for gap filling appears to be the only viable solution. A through-hole is then formed in a dielectric layer to expose an underlying metal feature, wherein the metal feature serves as a landing pad occupying the entire bottom of the through-hole. Upon filling the through-hole with conductive material, such as a metal plug to form a conductive via, the entire bottom surface of the conductive via is in direct contact with the metal feature. Such a conventional technique is illustrated in FIG. 3, wherein metal feature 30 of a first patterned metal layer is formed on first dielectric layer 31 and exposed by through-hole 32 formed in second dielectric layer 33. In accordance with conventional practices, through-hole 32 is formed so that metal feature 30 encloses the entire bottom opening, thereby serving as a landing pad for metal plug 34 which fills through-hole 32 to form conductive via 35. Thus, the entire bottom surface of conductive via 35 is in direct contact with metal feature 30. Conductive via 35 electrically connects metal feature 30 and metal feature 36 which is part of a second patterned metal layer. As shown in FIGS. 2 and 3, the side edges of a metal feature or conductive line, e.g., 30A, 30B, and 36A, and 36B, taper somewhat as a result of etching.
The reduction of design features to the range of 0.25 microns and under requires extremely high densification. The conventional practice of forming a landing pad completely enclosing the bottom surface of a conductive via utilizes a significant amount of precious real estate on a semiconductor chip which is antithetic to escalating high densification requirements. In addition, it is extremely difficult to voidlessly fill through-holes having such reduced dimensions because of the extremely high aspect ratio, i.e., height of the through-hole with respect to diameter of the through-hole. Accordingly, conventional remedial techniques comprise purposely widening the diameter of the through-hole to decrease the aspect ratio. As a result, misalignment occurs wherein the bottom surface of the conductive via is not completely enclosed by the underlying metal feature. This type of via is called a "borderless via", which also conserves chip real estate.
The use of borderless vias, however, creates new problems. For example, as a result of misalignment, the SOG gap filling layer is penetrated by etching when forming a misaligned through-hole, due to the low density and poor stability of SOG. As a result of such penetration, moisture and gas accumulate thereby increasing the resistance of the interconnection. Moreover, spiking can occur, i.e., penetration of the metal plug to the substrate causing a short. Adverting to FIG. 4, first dielectric layer 41 is formed on substrate 40 and a first metal pattern comprising a first metal feature, e.g., metal line 45, comprising anti-reflective coating 45A, is formed on first dielectric layer 41 gap filled with SOG 42. Dielectric layer 43 is then deposited and a misaligned through-hole formed therein exposing a portion of the upper surface and at least a portion of a side surface of metal line 45, and penetrating into and exposing a portion of SOG layer 42. Upon filling the through-hole with a metallic plug 44, typically comprising an initial barrier layer (not shown) and tungsten, spiking occurs, i.e., penetration through to substrate 40, thereby causing shorting.
Hydrogen silsesquioxane (HSQ) offers many advantages for use in interconnect patterns. HSQ is relatively carbon free, thereby avoiding poison via problems. Moreover, due to the virtual absence of carbon, it is not necessary to etch back HSQ below the upper surface of the metal lines to avoid shorting. In addition, HSQ exhibits excellent planarity and is capable of gap filling interwiring spacings less than 0.15 microns employing conventional spin-on equipment. HSQ undergoes a melting phase at approximately 200.degree. C., but does not convert to the high dielectric constant glass phase until reaching temperatures of about 400.degree. C. for intermetal applications and about 700.degree. C. to about 800.degree. C. for premetal applications. In copending application Ser. No. 08/992,430, filed on Dec. 18, 1997, a method is disclosed for selectively heating portions of a deposited HSQ layer adjoining a metal feature to increase the resistance of such adjoining portions to penetration when etching a misaligned through-hole for a borderless via.
However, HSQ is susceptible to degradation during processing leading to various problems, such as voids when forming borderless vias. For example, when forming a borderless via, a photoresist mask is deposited and a misaligned through-hole etched to expose a portion of an upper surface and a portion of a side surface of an underlying metal line, and penetrate into and expose the HSQ layer. Etching to form the through-hole is typically conducted employing reactive ion etching with fluorocarbon chemistry, e.g., CF.sub.4, with attendant polymer formation. The photoresist mask is then stripped, typically employing an oxygen (O.sub.2)-containing plasma. After the photoresist mask is plasma stripped, the through-hole is conventionally cleaned, employing a wet solvent, to remove polymers formed during reactive ion etching. Solvents conventionally employed include ACT935.TM. and ACT970.TM. available from Ashland Chemical Company in Pennsylvania. A further plasma stripping step is conventionally conducted after wet solvent cleaning.
During experimentation assessing the feasibility of employing HSQ for gap filling in interconnection patterns comprising a borderless via, it was found that the HSQ gap fill layer absorbs water during solvent cleaning of the misaligned through-hole. It was further found that upon subsequent filling of the through-hole, as with a barrier metal, such as titanium nitride or titanium-titanium nitride, followed by tungsten, outgassing occurs whereby voids are generated not only in the portion of the borderless via along a side surface of the lower metal feature, but throughout the borderless via. Such outgassing was also found to inhibit barrier metal adhesion resulting in undesirable interaction between tungsten hexafluoride, employed to deposit the tungsten, and the aluminum or aluminum alloy primary conductive layer of the lower metal feature.
In view of the manifest advantages of HSQ, there exists a need to provide technology whereby HSQ can be employed for voidless gap filling in forming interconnection patterns containing substantially voidless, high integrity borderless vias.